Abstract: This paper presents a design technique of CNTFET based 1-Bit Arithmetic Logical Unit (ALU) using Domino Logic. Domino Logic offers smaller area and higher speed than Static Logic design. In this paper circuit performance of CNTFET based Domino logic 1-Bit ALU is compared with Static Logic 1-Bit ALU. The simulation results calculated using HSPICE have reported to show 38.6% reduction in delay and 12.8% reduction in area for Domino Logic as compared to Static Logic 1-Bit ALU(Full Adder Logic) at 32nm technology. For Optimization of CNTFET based Domino Logic 1-Bit ALU various parameters like diameter, temperature and pitch are varied at 32nm technology. The proposed Domino Logic 1-Bit ALU(Full Adder Logic) has shown reduction in Power Delay Product by 33.2% at 5nm pitch as compared to Domino logic 1-Bit ALU(Full Adder Logic) at 20nm pitch with CNT diameter at 1.487nm, 27? temperature and a reduction of 94.2% at 1.0179nm CNT diameter and 5nm pitch.

Keywords: ALU, CNTFET, Dynamic Logic, Domino Logic, Full Adder, Static Logic.